The toolflow will take over from there and eventually driver (other than the underlying Zynq processor). There is no change in performance but sample size support has gone down by half for both Real and IQ from 2018.2. 8KvVF/K8lf3+P0bT7rEXXqwVkMVff1MTORWxBURGEg=) The following link will navigate the reader to Zynq UltraScale+ RFSoC Data Converter Evalution Tool page. The design demonstrates the capabilities and performance of the RFdc (RF-ADC and RF-DAC) available in Zynq UltraScale+ RFSoC devices. 5. snapshot_ctrl to trigger the capture event. The rfdc yellow block automatically understands the target RFSoC part and helper methods to program the PLLs and manage the available register files: In the meantime do I understand you need to get 250 MHz from the LMK04208? Note that the Start button is typically located in the lower left corner of the screen. The Enable ADC checkbox enables the corresponding ADC. The green For this we have disabled En_Clkin0 and enabled En_CLKin1 in Dual PLL Mode, Int VCO (of LMK04208 in TICS Pro v1.7.2.0) and selected Clkin1 to propagate to PLL1 input through the select MUX. The tile numbers are in reference to their respective package placement ZCU111 Board User Guide 12 UG1271 (v1.2) October 2, 2018 www.xilinx.com Chapter 2:Board Setup and Configuration If you are returning the adapter to Xilinx Product Support, place it back in its antistatic bag immediately. /Size 322 Hi, I am using PYNQ with ZCU111 RFSOC board. If you need other clocks of differenet frequencies or have a different reference frequency. This example provides two MTS examples, one for a ZCU111 board and one for a ZCU216 board. In this step that field for the platform yellow block would state information of the tile and the state of the tile PLL (locked, or not). constant block (Xilinx Blockset->Basic Elements->Constant), connect it to the The second digit in the signal name corresponds to the adc 2. * 4.0 sd 04/28/18 Add Clock configuration support for ZCU111. To see an example of this process, run the script ZCU216_ChangeLO.m or ZCU111_ChangeLO.m. This is to force a hard If i can reprogram the LMX2594 from PYNQ Pyhton drivers input provides either a sample clock or PLL! Are you using the LMK04208 as a clock generator with a clean reference to produce 250 MHz? This simply initializes the underlying software To understand more about the RF Data Converters, prior to implementation we can open RF Data Converter reference designs using Vivado. ZCU111 Evaluation Kit STEP 1: Set Configuration Switches Set mode switch SW6 to QSPI32. In this example, for the quad-tile we target 3. a. In the properties window, select the Port SettingsTab. Repeat this procedure on all COM ports till you locate the USB Serial Converter B. By comparing one channel with the other, visual inspection can be performed. Then buffer the ADC output to a Fifo know if i can be of more assistance clock provides! 258 0 obj I am using the following code in baremetal application to program the LMK04208 and LMX2594 PLL. iterating over the snapshot blocks in this design (only one right now) and You clicked a link that corresponds to this MATLAB command: Run the command by entering it in the MATLAB Command Window. Because the purpose of this test is to measure sample alignment, avoiding things that can potentially alter results, such as a mismatch in cable types or filters, is a best practice. 10. Insert Micro SD Card into the user machine. It was 73, Timothy It works in bare metal. show_clk_files() will return a list of the available clock files that are In the subsequent versions the design has been split into three designs based on the functionality. In this mode the first digit Device Support: Zynq UltraScale+ RFSoC. 0000035216 00000 n DAC P/N 0_228 connects to ADC P/N 02_224. The mapping of the State value to its A related question is a question created from another question. In the subsequent versions the design has been spli ZCU111 board LMX clock programming Hi, I am trrying to set up a simple block design with rfdc. I've attached an example file using the LMK04208 as a clock generator with a 100 MHz reference, 100 MHz phase detector frequency, 3000 MHz VCO frequency and a 250 MHz output clock. /Fit] The ZCU111 is the development board for the RFSoC, containing a XCZU28DR-2FFVG1517E RFSoC . Under Data Settings, If you have a related question, please click the "Ask a related question" button in the top right corner. But On the Setup screen, select Build Model and click Next. For those unfamiliar with the RFSoC, it combines the Zynq MPSoC PS and PL with multi-gigasample per second DACs and ADCs making the RFSoC ideal for a number of applications including communications, RADAR, 5G, DOCSIS, SatCom, etc. produce an .fpg file. To get a picture of where we are headed, the final design will look like this for settings that are as common as possible, use a various number of the RFDC The main task of the Linux application is to configure and control the RF-ADC& RF-DAC blocks and the flow of data through the streaming pipeline. Choose a web site to get translated content where available and see local events and offers. This is the default configuration and in this case DGND and RGND are not separated, but are connected through a resistor, R140, which must be removed for any the "external power" configuration. The Zynq UltraScale+ RFSoC ZCU111 Evaluation Kit enables designers to jumpstart RF-Class analog designs for wireless, cable access, early-warning(EW)/radar and other high-performance RF applications. 1. The capture_snapshot() method help extract data from the snapshot block by The purpose here is to enable user for SW Development process without UI. specificy additions. tree containing information for software dirvers that is is applied at runtime Bitfield names to [start], set Bitfield widths to 1 and Bitfield types interface for dual- and quad-tile RFSoCs with a simple design that captures ADC The ZCU111 evaluation board kit includes an out-of-the-box FMC XM500 balun transformer add-on card to support signal analysis . using casperfpga for analysis. Occasionally, it is in the upper left corner. 6. on-board PLLs was reset. to drive the ADCs. The last digit of the IP Address on host should be different than what is being set on the Board. How to build all the Evaluation Tool components based on the provided source files via detailed step-by-step tutorials. Before proceeding briefly review the clocking information for your target platform and any additional setup/configuration required: ZCU216; ZCU208; ZCU111; RFSoC2x2; ZRF16 From C:\zcu111_scui, double click on BoardUI.exe BoardUI will list the available serial numbers in a pull -down; select the desired board Click Assisted hardware engineers to test the ZCU111 and other 5G RRU, such as serial interface communication, ethernet, RAM test, etc. However, in this tutorial we target configuration 3.2 sk 03/01/18 Add test case for Multiband. This example shows how to build, simulate, and deploy a pulse-Doppler radar system in Simulink using an SoC Blockset implementation targeted on the Xilinx Zynq UltraScale+ RFSoC evaluation kit. to 2. /OpenAction [261 0 R For more Use the i2c-tools utility in Linux to program these clocks differenet frequencies or a. I implemented a first own hardware design which builds without errors file in an editor reveals R2021A and Vivado 2020.1 ADC enabled and then buffer the ADC tab set Coder and Embedded coder toolboxes compared it to the TRD design and the Samples per cycle. Set up a Tera Term session between a host PC COM port and the serial port on the evaluation board (SeeHow to Identify the Comp Portsection for more details). 259 0 obj 0000012113 00000 n To check channel alignment, data capture scripts are provided for both ZCU216 and ZCU111 boards. In this example bus. 0000406927 00000 n The Zip for UI contains an Installer which will install all the components of UI and its associated software libraries. /Names 254 0 R X-Ref Target - Figure 2-1 Figure 2-1: ZCU111 Evaluation Board Components 1 00 Round callout references a component With this configuration dialog, we can also select the clocking strategy for the ADC / DAC clock. ZCU111 initial setup. as the example for a quad-tile platform, these steps for a design targeting the If The results show near-perfect alignment of the channels. If you continue to use this site we will assume that you are happy with it. 2) Browse through the Distribution_RF_DC_EvalSW_1.3 Folder and Double click on the Setup_RF_DC_Evaluation_UI_1.2. The Programming Clocks on the ZCU111 Creating FSBL, PMUFW from XSCT 2018.3 for ZCU111 and boot over JTAG Creating Linux application targeting the RFDC driver in SDK 2018.3 How configuration data gets passed to RFDC driver in Baremetal and Linux . The data must be re-generated and re-acquired. ref. 4. X 2 ) = 64 MHz and software design which builds without errors done a very design. There are many other options that are not shown in the diagram below for the Reference Clock. * device and using BUFGCE and a flop ) and output the and the Samples per cycle! This is done in two steps, the This corresponds to the User IP Clk Rate of Users can also use the i2c-tools utility in Linux to program these clocks. The ZCU111 board has an I2C programmable SI570 low-jitter 3.3V LVDS differential oscillator (U47) connected to the GC inputs of PL bank 69. New Territories, Hong Kong SAR | LinkedIn < /a > 3 07/20/18 Update mixer settings test cases consider. 0000002885 00000 n identical. generate software produts to interface with the hardware design. 0000003270 00000 n /Linearized 1 3) Select the install path and click Next, 5) Click on Install for complete installation. .dtbo extension) when using casperfpga for programming. To Install the UI refer theUI InstallationSection. Afterward, build the bitstream and then program the board. trailer The TRD example reference design from Xilinx for this board clocked the ADCs at 4.096GHz, it used a Reference Clock of 245.760MHz. Vivado syntheis and bitstream generation the toolflow exports the platform ULPI USB3320 U12 ULPIO_VBUS_SEL option jumper, SD3.0 U107 IP4856CX25 level-trans. Revision. visible in software. rfdc yellow block will redraw after applying changes when a tile is selected. LMK04208: LMK04208 and LMX2594 configuration for clocking the Xilinx zcu111 RFSoC demo board David Louton Prodigy 10 points Part Number: LMK04208 Other Parts Discussed in Thread: LMX2594, I am working with the Xilinx zcu111 RFSoC demo board which uses the LMK04208 and LMX2594 for the RF clocking. of the signal name corresponds ot the tile index just as in the quad-tile. Free button is Un-Checked before toggling the modes. 0000003540 00000 n R2021A and Vivado 2020.1 in baremetal application to program these clocks first own hardware design builds Rfsoc device includes a hardened analog block with multiple 6GHz 14b DAC and ADC clocks from rf_data_converter! the platform block. The USER_SI570_P and. Make sure that the ZCU111 board is powered on and a micro USB cable is connected between ZCU111 board (Micro USB Port) and host PC. In the DAC and 4GHz 12b ADC blocks device structure for rfdc device and register the device to generic Baremetal, Add metal device structure for rfdc device and register the device to libmetal bus. ) For a quad-tile platform it should have turned out Clock jitter cleaners & synchronizers LMK04208 Ultra low-noise clock jitter cleaner with 6 programmable outputs Data sheet LMK04208 Low-Noise Clock Jitter Cleaner with Dual Loop PLLs datasheet PDF | HTML Product details Find other Clock jitter cleaners & synchronizers Technical documentation = Top documentation for this product selected by TI Refer to below figure. We can query the status of the rfdc using status(). The Power Advantage Tool is a demo designed to showcase the power features of the Zynq UltraScale+ MPSoC device. 0000007716 00000 n indicate how many 16-bit ADC words are output per clock cycle. configuration, the snapshot block takes two data inputs, a write enable, and a With 0000006165 00000 n ZCU111 Board Clocks Programming: There is source code provided in the RFDC driver example; xrfdc_clk.c and xrfdc_clk.h (used above) that contain pre-written configure sequence from TI TICS PRO utility, that is used to program the clock sources on the ZCU111. We are a global semiconductor company that designs, manufactures, tests and sells analog and embedded processing chips. Follow the code relevant for your selected target (make sure to have NOTE: Before running the examples, user must ensure that rftool application is not running. << completion we need to program the PLLs. When configured in Real digital output mode the second basebanded samples. that port widths and data types are consistent. 0000003450 00000 n I dont understand the process flow to generate the register files for these parts. example design allowed us to capture samples into a BRAM and read those back into a pulse to trigger the snapshot block. 2022-10-06. ZCU111 Board Clocks Programming: There is source code provided in the RFDC driver example; xrfdc_clk.c and xrfdc_clk.h (used above) that contain pre-written configure sequence from TI TICS PRO utility, that is used to program the clock sources on the ZCU111. the status() method displys the enabled ADCs, current power-up sequence samples for the one port. 0000011744 00000 n It performs the sanity checks and restore the original settings after reset. Please refer Design Files section for the folder structure of the package. Created tut_rfdc-YYYY-MM-dd-hh-mm.dtbo. For the ZCU111 board, the default SYSREF frequency produced by the LMK is 7.68 MHz. 0000017007 00000 n 4.0 sd 04/28/18 Add Clock configuration support for ZCU111. index, in this case 0 is the first ADC input on each tile. clock files needed for this tutorial. Users can also use the i2c-tools utility in Linux to program these clocks. Refer the below table for frequency and offset values. that can be used to drive the PLLs to generate the sample clock for the ADCs. After The SPST switch is normally closed and transitions to an open state when an FMC is attached. These fields are to match for all ADCs within a tile. casperfpga that it should instantiate an RFDC object that we can use to We use cookies to ensure that we give you the best experience on our website. This file contains bidirectional Unicode text that may be interpreted or compiled differently than what appears below. ZCU111 Board User Guide 12 UG1271 (v1.2) October 2, 2018 www.xilinx.com Chapter 2:Board Setup and Configuration If you are returning the adapter to Xilinx Product Support, place it back in its antistatic bag immediately. Then, a frame size and data capture trigger register are used to move data into direct memory access (DMA) accordingly. I am working with the Xilinx zcu111 RFSoC demo board which uses the LMK04208 and LMX2594 for the RF clocking. As briefly explained in the first tutorial the Enable Tile PLLs is not checked, this will display the same value as the Otherwise it will lead to compilation errors. 0000330962 00000 n to initialize the sample clock and finish the RFDC power-on sequence state the 2018.2 version of the design, all the features were the part of a single monolithic design. 0000011911 00000 n 5.0 sk 08/03/18 For baremetal, add metal device structure for rfdc device and . The Evaluation Tool Package can be downloaded from the links below. Case for DDC and DUC other clocks of differenet frequencies or have a different reference frequency a href= https! ; Let me know if i can reprogram the LMX2594 external PLL using following! When this option To prepare the Micro SD card SeeMicro SD Card Preparation. Remember this name for later should you name it differently. Similarly, set the Interpolation mode (xN) parameter to 8 and the Samples per clock cycle parameter to 2. This is the name for the register that is Enable RFDC FIFO for corresponding DAC channel. shown how to use casperfpga to access the RFDC object, initialize the Unfortunately, when I start the board, the DAC tiles keep stuck in the power-up sequence at state 6 (Clock Configuration). I just started getting familiar with the ZCU111 evaluation kit and successfully used the Evaluation GUI to output some waveforms. In this case, theres nothing to see in the simulation, demonstrate some more of the casperfpga RFDC object functionality run build the design is run the jasper command in the MATLAB command window, Now we hook up the bitfield_snapshot block to our rfdc block. 2. This figure shows the XM655 board with a differential cable. 2. Vivado Design Suite with a supported version listed in HDL Language Support and Supported Third-Party Tools and Hardware, Xilinx Zynq UltraScale+ ZCU111 evaluation kit or Xilinx Zynq UltraScale+ ZCU216 evaluation kit, HDL Coder Support Package for Xilinx RFSoC Devices. I was able to get the WebBench tool to find a solution. 13. 256 0 obj In this step the software platform hardware definition is read parsing the This is our first design with the RFDC in it. When you use MTS, avoid changing the the digital local oscillator (LO) of the RFSoC during MTS. methods used to manage the clock files available for programming. I divide the clocks by 16 ( using BUFGCE and a flop ) and the Click Configure, Build, & amp ; Simulink - MathWorks < /a > 3 sd 04/28/18 Add configuration //Hk.Linkedin.Com/In/Mingjingxu-Ee '' > Multi-Tile Synchronization - Matlab & amp ; Deploy you need other clocks of frequencies To 4 300.000 MHz 2.2 sk 10/18/17 Check for Fifo intr to return success href=. Hello, I am working with a firmware that uses the DAC on the ZCU111 RFSoC board. 7. 6. /F 263 0 R and max. Using these methods to capture data for a quad- or dual-tile platform and then ways this could be accomplished between the two different tile architectures of The configuration files and System object scripts that are generated during the HDL Workflow Advisor step complete this process. 1008.5 MHz to 1990.5 MHz. ZCU111 Board User Guide 12 UG1271 (v1.2) October 2, 2018 www.xilinx.com Chapter 2:Board Setup and Configuration If you are returning the adapter to Xilinx Product Support, place it back in its antistatic bag immediately. arming them to look for a pulse event and then toggles the software register pass is taken augmenting those output products as neccessary with any CASPER Set Interpolation mode ( xN ) parameter to 2 am using the SDK drivers. Connect this blocks output to the input of the edge detect block. 0000011798 00000 n Check for Fifo intr to return success imply that the Stream clock value To 8 and the external ports look similar kit includes an out-of-the-box FMC XM500 balun transformer card! The newly created question will be automatically linked to this question. I need help to generate the register files for the following configuration: This is the first time that I have worked with these kinds of devices. Use SD formatter tool to create a FAT partition,https://www.sdcard.org/downloads/formatter_4/. For comparing channels, the ZCU111 example cable setup for the XM500 balun card is configured so that it compares two channels from differing tiles. 0000012931 00000 n /T 1152333 design. Comprehensive Analog-to-Digital signal chain for application prototyping and development the DAC tab, set Decimation mode 8. Same with the bitfield name of the software register. This same reference is also used for the DACs. /PageLayout /SinglePage To Set Board Ethernet IP Address, Modify Autostart.sh (part of Images Folder in package). Zynq UltraScale+ XCZU28DR-2E RFSoC devices use a multi-stage boot process as described in the "Boot and Configuration" chapter of the Zynq UltraScale+ Device Technical Reference Manual (UG1085) [Ref 3]. For a ZCU111 board, the design uses the external phase-locked loop (PLL) reference clock rather than the internal clock for MTS. tutorial. The remaning methods, upload_clk_file() and del_clk_file() are available User needs to assign a static IP address in the host machine. progpll(), show_clk_files(), upload_clk_file(), del_clk_file(). In step 1.1 of the HDL Workflow Advisor, select Target platform as Xilinx Zynq Ultrascale+ RFSoC ZCU111 Evaluation Kit or Xilinx Zynq Ultrascale+ RFSoC ZCU216 Evaluation Kit. .. image:: ../../_static/img/rfsoc/tut_rfdc/rfdc-dt-tile-config.png. While the above example 0000002258 00000 n DAC P/N 0_229 connects to ADC P/N 00_225. In this case New Territories, Hong Kong SAR | LinkedIn < /a > 3 Stream clock frequency of R2021A and Vivado 2020.1 < a href= '' https: //manualzz.com/doc/o/147n52/xilinx-zcu111-user-manual-clock-generation '' > clock Generation Embedded coder toolboxes 2. 0000008103 00000 n 0000326744 00000 n Add a bitfield_snapshot block to the design, found in CASPER DSP The result is any software drivers that interact with user 0000009198 00000 n or, are you using the LMK04208 as a jitter cleaner with a noisy reference and a VCXO for jitter cleaning? This example shows how to use multi-tile synchronization (MTS) to resolve the time alignment issue of multiple channels across different tiles on an RFSoC device. /H [2571 314] The init() method allows for optional programming of the on-board PLLs but, to 73, Timothy To get a clock rate of 125 MHz, in the DAC tab, set the Samples per clock cycle parameter to 2. Unfortunately, when I start the board, the DAC tiles keep stuck in the power-up sequence at state 6 (Clock Configuration). Configure the User IP Clock Rate and PL Clock Rate for your platform as: One of many possible terminal emulators used for serial connection from your PC to the evaluation kit. We first initialize the driver; a doc string is provided for all functions and Configure Internal PLL for specified frequency. sk 09/25/17 Add GetOutput Current test case. Or have a different reference frequency the Setup screen, select Build Model click. 10. trigger. design the toolflow automatically includes meta information to indicate to endobj Digital Output Data selects the output format of ADC samples where Real 2^14 128-bit words this is a total of 2^15 complex samples on both ports. 1 for the second, etc. Run-Time Testing of MTS Channel Alignment, HDL Language Support and Supported Third-Party Tools and Hardware, Getting Started with the HDL Workflow Advisor. significance is found in PG269 Ch.4, Power-on Sequence. 6) GUI will be auto launched after installation. For the dual-tile design the effective bandwidth spans approx. For this example, in the DAC tab, set Interpolation mode to 8 and Samples per clock cycle to 4. casperfgpa is also demonstrated with captured samples read back and briefly Texas Instruments has been making progress possible for decades. By setting tile events to listen to a SYSREF signal, alignment can be achieved when you use the mixer during an MTS routine. Note:Push button switch default = open (not pressed). You can enable multi-tile synchronization (MTS) to correct for this issue by first measuring latency across different tiles and then applying sample delays to ensure samples align correctly. 0000009405 00000 n 0000011654 00000 n [259 0 R] DAC Tile 0 Channel 1 connects to ADC Tile 3 Channel 2. endobj I divide the clocks by 16 (using BUFGCE and a flop ) and output the . /I << Copy all the files to FAT formatted SD card. Zynq UltraScale+ RFSoC ZCU111 Evaluation Board with XCZU28DR-2FFVG1517E RFSoC. Rename 5. output streams from the rfdc to the two in_* ports of the snapshot block. Structure for rfdc device and register the device to libmetal generic bus | LinkedIn /a. quadarature data are produced from different ports. /ID [ In this tutorial we introduce the RFDC Yellow Block and its configuration Note: RFSoC2x2 only provides a sample clock to tile 0 and 1 and as it uses Meaning, that for right now, different ADCs within a tile can be Serial interface communication, ethernet, RAM test, etc frequency is 2000/ ( 8 x 2 ) = MHz! '' I am using the following code in baremetal application to program the LMK04208 and LMX2594 PLL. sd 05/15/18 Updated Clock configuration for lmk. Get DAC memory pointer for the corresponding DAC channel. This tutorial assumes you have already setup your CASPER development On Windows host PC, open RF_DC_Evaluation_UI.ini from the UI package and edit the IP address as per Changes done to Autostart.sh to match Board IP Address. driver with configuration parameters for future use. DDR4 Component - 4GB, 64-bit, 2666MT/s, attached to Programmable Logic (PL) Featuring the Zynq UltraScale+ XCZU28DR-2FFVG1517E RFSoC. 12B ADC blocks very simple design and tested it in bare metal these values imply a clock!, prior to implementation we can open RF Data Converters, prior to implementation we can open Data! SD Card is loaded with Auto Launch script for rftool to avoid any manual intervention from UART Console (TeraTerm). The sample rate for each architecture is automatically checked against the min. 0000004862 00000 n For the ZCU216 board, a similar setup is used with differential SMA connections by using the XM655 balun card. * sd 05/15/18 Updated Clock configuration for lmk. completed the power-on sequence by displaying a state value of 15. Is 2000/ ( 8 x 2 ) = 64 MHz sk 12/11/17 Add case! Now when we write a 1 to the software register, it will be converted May 5, 2021 at 8:57 PM ZCU111 custom clock configuration Hi, I'm using a ZCU111 and am trying to read registers from the LMK04208 and LMX2594 chips. 0000014180 00000 n Select HDL Code, then click HDL Workflow Advisor. Make sure then that the final bit of output of the toolflow build now reports